Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder

Shikha Singh, Yagnesh B. Shukla


Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumption of 1.7 µW and power delay product (PDP) of 57.3 fJ, the results demonstrate that the Wallace multiplier design employing CSA with first zero finding logic (FZF) logic has the lowest power consumption of 1.4 µW and PDP of 27.5 fJ.


binary to excess -1 convertor; energy delay product; first zero finding logic; low-power multiplier; power delay product;

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TELKOMNIKA Telecommunication, Computing, Electronics and Control
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