Non-Planar MOSFET Modeling with Analytical Approach

Munawar A Riyadi, Darjat Darjat, Teguh Prakoso, Jatmiko E. Suseno


Non-planar structures have been identified as promising structure for next device generation in the nanoelectronic era. However, the continuous device dimension scaling into nano regime eventually requires more sophisticated model due to the limitation of the existing models. A model for non-planar MOSFET structure was elaborated in this paper, especially for device with pillar structure, using analytical approach. The concern of channel shape and structure were discussed as well. The result shows the shift in subthreshold characteristic in the channel with recessed channel model. The charge sharing is suspected as one of the key parameter in the shift of performance in the recessed region.

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International Technology Roadmap for Semiconductors (ITRS) - 2009. Available:

T. Endoh, et al., "Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET," IEICE Transactions on Electronics, vol. E93-C, pp. 557-562, 2010.

A. Sugimura, et al., "Proposal of Vertical-Channel Metal Oxide Semiconductor Field-Effect Transistor with Entirely Oxidized Silicon Beam Isolation," Japanese Journal of Applied Physics, vol. 48, Apr 2009.

M. A. Riyadi, et al., "Vertical Double Gate MOSFET For Nanoscale Device With Fully Depleted Feature," AIP Conference Proceedings, vol. 1136, pp. 248-252, 2009.

J. Pan, "The Gate-Controlled Diode, High-Frequency, and Quasi-Static C-V Techniques for Characterizing Advanced Vertical Trenched Power MOSFETs," IEEE Transactions on Electron Devices, vol. 56, pp. 1351-1354, Jun 2009.

M. Masahara, et al., "Vertical Ultrathin-channel Multi-gate MOSFETs (MuGFETs): Technological Challenges and Future Developments," IEEJ Transactions on Electrical and Electronic Engineering, vol. 4, pp. 386-391, May 2009.

L. Tan, et al., "The influence of junction depth on short channel effects in vertical sidewall MOSFETs," Solid-State Electronics, vol. 52, pp. 1002-1007, 2008.

J. Moers, "Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface," Applied Physics A: Materials Science & Processing, vol. 87, pp. 531-537, 2007.

Y. Taur, et al., "A continuous, analytic drain-current model for DG MOSFETs," IEEE Electron Device Letters, vol. 25, pp. 107-109, 2004.

Y. Taur, "An analytical solution to a double-gate MOSFET with undoped body," IEEE Electron Device Letters, vol. 21, pp. 245-247, 2000.

X. P. Liang and Y. Taur, "A 2-D analytical solution for SCEs in DG MOSFETs," IEEE Transactions on Electron Devices, vol. 51, pp. 1385-1391, Sep 2004.

J. He, et al., "A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region," Chinese Physics B vol. 20, Jan 2011.

K. Chandrasekaran, et al., "Compact modeling of doped symmetric DG MOSFETs with regional approach," in Workshop on Compact Modeling, NSTI-Nanotech, MA, USA, 2006, pp. 792 - 795.

D. Munteanu, et al., "Compact model of the quantum short-channel threshold voltage in symmetric Double-Gate MOSFET," Molecular Simulation vol. 31, pp. 831-837, Oct 2005.

S. Kolberg and T. A. Fjeldly, "2D Modeling of nanoscale DG SOI MOSFETs in and near the subthreshold regime," Journal of Computational Electronics vol. 5, pp. 217-222, 2006.

B. Subrahmanyam and M. J. Kumar, "Recessed source concept in nanoscale vertical surrounding gate (VSG) MOSFETs for controlling short-channel effects," Physica E-Low-Dimensional Systems & Nanostructures, vol. 41, pp. 671-676, Feb 2009.

X.-J. Zhang, et al., "Analytical analysis of surface potential for grooved-gate MOSFET," Chinese Physics, vol. 15, pp. 631-635, 2006.

Z. Ghoggali and F. Djeffal, "Analytical analysis of nanoscale fully depleted Double-Gate MOSFETs including the hot-carrier degradation effects," International Journal of Electronics, vol. 97, pp. 119-127, 2010.

F. Djeffal, et al., "Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges," Microelectronics Reliability, vol. 49, pp. 377-381, 2009.

H. Lu and Y. Taur, "An analytic potential model for symmetric and asymmetric DG MOSFETs," IEEE Transactions on Electron Devices, vol. 53, pp. 1161-1168, 2006.

B. Yu, et al., "Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs," IEEE Transactions on Electron Devices, vol. 54, pp. 2715-2722, 2007.

V. Venkataraman and S. Nawal, "Modeling and Simulation of Strained Silicon MOSFETs for Nanoscale Applications," Bachelor of Technology dissertation, Department of Electrical Engineering, Indian Institute of Technology Delhi, Delhi, 2006.

K. K. Young, "Short-channel effect in fully depleted SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 36, pp. 399-402, 1989.

X. Zhang, et al., "An Analytical Model for Threshold Voltage of Grooved-Gate MOSFET's [in Chinese]," Chinese Journal of Semiconductors, vol. 4, pp. 441-445, 2004.

E. Kreyszig, Advanced engineering mathematics, 9th ed.: Wiley, 2006.

B. Doris, et al., "Extreme scaling with ultra-thin Si channel MOSFETs," Electron Devices Meeting, 2002. IEDM'02. Digest. International, pp. 267-270, 2002.

J. Tanaka, et al., "A sub-0.1mm grooved gate MOSFET with high immunity to short-channel effects," in Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International, 1993, pp. 537-540.



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