Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology

Abstract

Serial peripheral interface (SPI) transfers the data between electronic devices like micro controllers and other peripherals. SPI consists of two control lines: select signal and clock signal, and two data lines: input and output. In single master-single slave, the communication is in between master and slave only which will make the design complex and costly, area will increase. In regular SPI mode, the number of chip-select lines is increased if the number of slaves increases. Due to this, the input data received by the master from the slaves are corrupted at master input slave output (MISO). The proposed daisy chain method is used to overcome this problem. The daisy chain method requires only one chip select line at master compared to the regular SPI mode. When the chip-select line is active low, all the slaves are active, and the clock is initiated to all the slaves to transfer the data from the master to the first slave through the master output slave input (MOSI). In this paper, the daisy-chain SPI is designed and developed using Verilog. The proposed design is verified using system Verilog (SV) and universal verification methodology (UVM) in QuestaSim.